Sorting on a mesh-connected parallel computer
Communications of the ACM
Introduction to VLSI Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
De bruijn communications networks.
De bruijn communications networks.
A complexity theory for VLSI
Area-efficient vlsi computation
Area-efficient vlsi computation
Density and reliability of interconnection topologies for multicomputers
Density and reliability of interconnection topologies for multicomputers
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing
IEEE Transactions on Computers
A Group-Theoretic Model for Symmetric Interconnection Networks
IEEE Transactions on Computers
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
The de Bruijn multiprocessor network: a versatile sorting network
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
| Hi-index | 0.01 |
This paper presents a multiprocessor network architecture suitable for VLSI implementation. The proposed class of architectures is based on De Bruijn graphs which are distinct from the well-studied shuffle-exchange graphs. Compared to these latter De Bruijn graphs possess a smaller diameter and a greater fault-tolerance. The proposed architectures are shown to be suitable for efficient execution of parallel algorithms such as the N-point fast Fourier transform (FFT). It is shown that any VLSI layout of the proposed networks requires an area of atleast &Ohgr;(N2/logN), thus, providing a lower bound which is greater than that for shuffle-exchange graphs. Two procedures for laying out these networks on a VLSI chip are presented. The first procedure produces an O(N2/logN)-area layout and has a time complexity of O(N). The second procedure also produces an O(N2/logN)-area layout with good aspect ratio close to unity (for small N).