Communications of the ACM - Special section on computer architecture
The connection machine
Advanced computer architecture
Advanced computer architecture
Hypernet: A communication-efficient architecture for constructing massively parallel computers
IEEE Transactions on Computers
Cube structures for multiprocessors
Communications of the ACM
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Hierarchical Interconnection Networks for Multicomputer Systems
IEEE Transactions on Computers
On Hypercube-based hierarchical interconnection network design
Journal of Parallel and Distributed Computing
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Concrete Math
A multiprocessor network suitable for single-chip VLSI implementation
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
De bruijn communications networks.
De bruijn communications networks.
A New Family of Cayley Graph Interconnection Networks of Constant Degree Four
IEEE Transactions on Parallel and Distributed Systems
WICI: An Efficient Hybrid Routing Scheme for Scalable and Hierarchical Networks
IEEE Transactions on Computers
Sep: A Fixed Degree Regular Network for MassivelyParallel Systems
The Journal of Supercomputing
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
IEEE Transactions on Parallel and Distributed Systems
On the area of hypercube layouts
Information Processing Letters
IEEE Transactions on Parallel and Distributed Systems
Cyclic Networks: A Family of Versatile Fixed-Degree Interconnection Architectures
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Bidirectional versus Unidirectional Networks: Cost/Performance Trade-Offs
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Hyper-Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Self-healing in binomial graph networks
OTM'07 Proceedings of the 2007 OTM Confederated international conference on On the move to meaningful internet systems - Volume Part II
KCube: A novel architecture for interconnection networks
Information Processing Letters
HPGRID: a novel architectural model for resource management systems
Proceedings of the 2011 International Conference on Communication, Computing & Security
Topological properties of hierarchical interconnection networks: a review and comparison
Journal of Electrical and Computer Engineering
Feedback vertex sets in rotator graphs
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V
International Journal of Computer Applications in Technology
KMcube: the compound of Kautz digraph and Möbius cube
Frontiers of Computer Science: Selected Publications from Chinese Universities
DVcube: A novel compound architecture of disc-ring graph and hypercube-like graph
Theoretical Computer Science
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Introduces a class of hierarchical networks that is suitable for implementation of largemulti-computers in VLSI with wafer scale integration (VLSI/WSI) technology. Thesenetworks, which are termed dBCube, employ the hypercube topology as a basic cluster,connect many of these clusters using a de Bruijn graph, and maintain the nodeconnectivity to be the same for all nodes product graph. The size of this class of regularnetworks can be easily extended by increments of a cluster size. Local communication, tobe satisfied by the hypercube topology, allows easy embedding of existing parallelalgorithms, while the de Bruijn graph, which was chosen for JPL's 8096-nodemultiprocessor, provides the shortest distance between clusters running different parts ofan application. A scheme for obtaining WSI layout is introduced and used to estimate thenumber of tracks needed and the required area of the wafer. The exact number of tracksin the hypercube and an approximation for the de Bruijn graph are also obtained.Tradeoffs of area versus static parameters and the size of the hypercube versus that ofthe de Bruijn graph are also discussed.