An Efficient Unsorted VLSI Dictionary Machine
IEEE Transactions on Computers
A multiprocessor network suitable for single-chip VLSI implementation
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Area-efficient vlsi computation
Area-efficient vlsi computation
Computational Aspects of VLSI
Fault Tolerance in Binary Tree Architectures
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
A Dictionary Machine (for VLSI)
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
IEEE Transactions on Computers - Fault-Tolerant Computing
IEEE Transactions on Computers
A Gracefully Degradable VLSI System for Linear Programming
IEEE Transactions on Computers
Fuzzy primary representations of fuzzy ideals
Information Sciences: an International Journal
A Modular Fault-Tolerant Binary Tree Architecture with Short Links
IEEE Transactions on Computers
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach
IEEE Transactions on Computers
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
On designing a reconfigurable modular fault-tolerant binary tree architecture
CSC '91 Proceedings of the 19th annual conference on Computer Science
Modular Fault-Tolerant Boolean N-Cubes
IEEE Micro
Implementing Degradable Processing Arrays
IEEE Micro
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
IEEE Transactions on Computers
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes
IEEE Transactions on Parallel and Distributed Systems
Design and Analysis of Fault-Tolerant Star Networks
ICPP '97 Proceedings of the international Conference on Parallel Processing
Sliding algorithm for reconfigurable arrays of processors
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Hi-index | 0.03 |
A new modular, fault-tolerant scheme is proposed for the binary tree architecture. The approach uses redundant modular fault- tolerant building blocks to construct the complete binary tree. The restructuring operation is local to each faulty module. The proposed scheme is shown to be more reliable and easier to implement than the existing fault-tolerant schemes.