Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
Architectural Yield Optimization for WSI
IEEE Transactions on Computers
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
IEEE Transactions on Computers - Fault-Tolerant Computing
IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
IEEE Transactions on Computers
Large-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types
IEEE Transactions on Computers
IEEE Transactions on Computers
What Designers of Bus and Network Architectures Should Know about Hypercubes
IEEE Transactions on Computers
A Channel-Constrained Reconfiguration Approach for Processing Arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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The locally redundant modular tree (LRMT) schemes offer high yield and reliability for trees of relatively few levels but are less effective for large binary trees due to the imbalance of reliability of different levels. A new multiple-level redundancy tree (MLRT) architecture that combines modular schemes with level-oriented schemes which lead to better yield and reliability is presented. The MLRT structure enhances the wafer yield to significant levels by offering separate layers of protection for random and clustered defects. Unlike most existing techniques, this technique performs a more accurate reliability analysis by taking into account both switch and link failures. A measure called the marginal switch to processing element area ratio (MSR) is introduced to precisely characterize the effect of switch complexity on the reliability of the redundant system. A systematic method for the optimal distribution of spare modules of the MLRT structure is also presented. The analyses show that the MLRT structure offers higher yield and system reliability than LRMT and subtree-oriented fault-tolerance (SOFT) structures do.