Communications of the ACM
Introduction to VLSI Systems
Wafer scale integration of configurable, highly parallel processors
Wafer scale integration of configurable, highly parallel processors
BVE: a wafer-scale engine for differential equation computation
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Fault simulation programs for integrated-circuit yield estimations
IBM Journal of Research and Development
Synergistic Fault-Tolerance for Memory Chips
IEEE Transactions on Computers
IEEE Transactions on Computers
Improved Yield Models for Fault-Tolerant Memory Chips
IEEE Transactions on Computers
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
IEEE Transactions on Computers
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits
IEEE Transactions on Computers
An Improved Analytical Yield Evaluation Method for Redundant RAM's
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
| Hi-index | 15.01 |
A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized.