A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Yield optimization in wafer scale circuits with hierarchical redundancies
Integration, the VLSI Journal
On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Architectural Yield Optimization for WSI
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
IEEE Transactions on Computers
Large-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
IEEE Transactions on Computers
IBM Journal of Research and Development
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors
Journal of Electronic Testing: Theory and Applications
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 14.98 |
Presents and analyzes a new multiple-level redundancy scheme based on hierarchical and element level redundancy for the enhancement of yield and reliability of large area array processors. This scheme can effectively tolerate not only the random defects/faults, but also the clustered defects/faults. The analysis presented here is general in that it takes into account the chip-kill defects occurring in the support circuit area of the array processors and is applicable to a variety of array processors. The authors derive bounds for the support circuit area which will be useful in selecting the most cost-effective redundancy scheme for a given application. The concept of subprocessing element-level redundancy is discussed and it is shown that a combination of subprocessing element-level redundancy with hierarchical redundancy offers significant yield improvements, especially for array processors with large area processing elements. The problem of optimal redundancy is also addressed.