Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
A Modular Fault-Tolerant Binary Tree Architecture with Short Links
IEEE Transactions on Computers
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors
IEEE Transactions on Computers - Special issue on fault-tolerant computing
IEEE Transactions on Computers
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
IEEE Transactions on Computers
Implementing Degradable Processing Arrays
IEEE Micro
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
Routing in Modular Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Design of a Circuit-Switched Highly Fault-Tolerant k-ary n-cube
ICPP '97 Proceedings of the international Conference on Parallel Processing
ADTS: an array defect-tolerance scheme for wafer scale gate arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A General Reconfiguration Technique for Fault Tolerant Processor Architectures
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences—Informatics and Computer Science: An International Journal
Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An improved replacement algorithm in fault-tolerant meshes
Proceedings of the 2007 Summer Computer Simulation Conference
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An efficient reconfiguration scheme for fault-tolerant meshes
Information Sciences: an International Journal
| Hi-index | 15.01 |
In the proposed scheme, spare PEs are located at interstitial sites within the array. Each spare can functionally replace any one of the neighboring primary PEs that are connected to it. Because spares are physically close to the PE that they replace, restructured interconnections are short, minimizing performance degradation. This structure can incorporate different levels of redundancy depending on how many of the interstitial sites are used to locate spares, and also how many spares are placed at each site. The author gives a polynomial time algorithm for assigning operational spares to failed primary PEs. He also gives area efficient layouts for such structures, and designs for implementing the switching network needed for reconfiguration. A procedure for deciding the optimum level of redundancy so as to maximize chip area utilization is also shown. The main attractive features of interstitial redundancy are short (fixed length) PE interconnections and high utilization of failure-free PEs. The analysis shows that for a wide range of array sizes and PE survival probabilities, 45-55 percent utilization of failure-free PEs on the chip can be achieved.