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Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
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In this paper, we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with {({\frac{k}{j}})}^n spare nodes. Each set of j^n regular nodes is connected to a spare node and the spare nodes are interconnected as either a ({\frac{k}{j}}){\hbox{-}}{\rm ary}n-cube if j \ne {\frac{k}{2}} or a hypercube of dimension n if j = {\frac{k}{2}}. Our approach utilizes the capabilities of the wave-switching communication modules of the spare nodes to tolerate a large number of faulty nodes. Both theoretical and experimental results are examined. Compared with other proposed schemes, our approach can tolerate significantly more faulty nodes with a low overhead and no performance degradation.