Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Introduction to VLSI Systems
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
The Reliability of Systems with Two Levels of Fault Tolerance: The Return of the 'Birthday Surprise'
IEEE Transactions on Computers
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
IEEE Transactions on Computers
Reconfiguration for fault tolerance using graph grammars
ACM Transactions on Computer Systems (TOCS)
An Efficient Method for Approximating Submesh Reliability of Two-Dimensional Meshes
IEEE Transactions on Parallel and Distributed Systems
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
Fault-tolerant recursive least-squares computations on a mesh-connected parallel processor
Journal of Parallel and Distributed Computing
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
IEEE Transactions on Computers
Adding Multiple-Fault Tolerance to Generalized Cube Networks
IEEE Transactions on Parallel and Distributed Systems
High-level synthesis of gracefully degradable ASICs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Totally defect-tolerant arrays capable of quick broadcasting
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A General Reconfiguration Technique for Fault Tolerant Processor Architectures
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
An improved replacement algorithm in fault-tolerant meshes
Proceedings of the 2007 Summer Computer Simulation Conference
Paper: Reconfigurable VLSI/WSI multipipelines
Parallel Computing
Self organization on a swarm computing fabric: a new way to look at fault tolerance
Proceedings of the 7th ACM international conference on Computing frontiers
Sliding algorithm for reconfigurable arrays of processors
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
| Hi-index | 4.12 |
Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.