Reconfiguration for fault tolerance using graph grammars

Authors:
M. D. Derk;L. S. DeBrunner
Affiliations:
Oklahoma City Univ., Oklahoma City, OK;Univ. of Oklahoma, Norman
Venue:
ACM Transactions on Computer Systems (TOCS)
Year:
1998

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Abstract

Reconfiguration for fault tolerance is a widely studied field, but this work applies graph grammars to this discipline for the first time. Reconfiguration Graph Grammars (RGG) are defined and applied to the definition of processor array reconfiguration algorithms. The nodes of a graph are associated with the processors of a processor array, and the edges are associated with those interprocessor communication lines that are active. The resulting algorithms for dynamic (run-time) reconfiguration are efficient and can be implemented distributively.