Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays
IEEE Transactions on Computers
The Connection Network Class for Fault Tolerant Meshes
IEEE Transactions on Computers
Reconfiguration for fault tolerance using graph grammars
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers
Efficient Self-Recovering ASIC Design
IEEE Design & Test
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays
IEEE Transactions on Computers
Computational Arrays with Flexible Redundancy
IEEE Transactions on Computers
On Dependability Evaluation of Mesh-Connected Processors
IEEE Transactions on Computers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A task remapping technique for reliable multi-core embedded systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A general approach to hardware recognition is proposed for VLSI/WSI fault-tolerant processor arrays. The technique, called full use of suitable spares (FUSS), uses an indicator vector, the surplus vector, to guide the replacement of faulty processors within an array. Analytical study of the general FUSS algorithm shows that there is a linear relationship between the array size and the area of interconnect required for reconfiguration to be 100% successful. In an instance of FUSS, called simple FUSS, reconfiguration is done by shifting up to or down the surplus vector's entries. The surplus vector is progressively updated after each column is reconfigured. The reconfiguration is successful when the surplus vector becomes null. Simple FUSS is discussed in detail and evaluated. Simulations show that when the number of faulty processors is equal to that of space processors, simple FUSS can achieve a probability of survival as high as 99%.