VLSI array processors
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Meshes with reconfigurable buses
Proceedings of the fifth MIT conference on Advanced research in VLSI
How to play bowling in parallel on the grid
Journal of Algorithms
New algorithms for reconfiguring VLSI/WSI arrays
Journal of VLSI Signal Processing Systems - Special issue: computer arithmetic
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance
IEEE Transactions on Computers
Reconfiguration Models and Algorithms for Stateful Interactive Processes
IEEE Transactions on Software Engineering
Escaping a grid by edge-disjoint paths
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
IEEE Transactions on Computers
Submesh Determination in Faulty Tori and Meshes
IEEE Transactions on Parallel and Distributed Systems
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Distributed Submesh Determination in Faulty Tori and Meshes
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
A Faster Algorithm for Finding Disjoint Paths in Grids
ISAAC '99 Proceedings of the 10th International Symposium on Algorithms and Computation
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Spare processor allocation for fault tolerance in torus-based multicomputers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Design of a highly reconfigurable interconnect for array processors
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Journal of Parallel and Distributed Computing
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast and efficient submesh determination in faulty tori
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
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Present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, the authors consider models that use multiple tracks along every channel and a single spare row (or column) of processing elements (PEs) along each boundary of the array. In the presence of faulty PEs the general methodology for reconfiguration involves replacing every faulty PE logically (rather than physically) by a spare PE through a sequence of logical substitutions; these sequences of substitutions are referred to as compensation paths. The authors show that if there exists a set of compensation paths subjected only to the constraints of continuity and nonintersection, then routing channels with three tracks are enough for the reconfiguration of the array. They refer to the underlying model as a S-track-l-spare model; this is done to distinguish it from other models that not only use multiple tracks but also multiple spare rows (or columns) along each boundary. An efficient algorithm for reconfiguration in our 3-track-1-spare model is presented and its performance evaluated. Experimental results show that the 3-track-1-spare model has much higher reconfiguration probability than other models that use considerably more spare processors