Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Fault Tolerance in VLSI Circuits
Computer
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
Efficient spare allocation in reconfigurable arrays
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
P-Complete Approximation Problems
Journal of the ACM (JACM)
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
IEEE Transactions on Computers
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays
IEEE Transactions on Computers
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Scalable,Low Cost Design-for-Test Architecture for UltraSPARC" Chip Multi-Processors
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Approach for Torus Embedding
ICPP '99 Proceedings of the 1999 International Workshops on Parallel Processing
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Mapping Strategies for Switch-Based Cluster Systems of Irregular Topology
ICPADS '01 Proceedings of the Eighth International Conference on Parallel and Distributed Systems
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Overlay Networks: A Scalable Alternative for P2P
IEEE Internet Computing
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
Exploiting Microarchitectural Redundancy For Defect Tolerance
ICCD '03 Proceedings of the 21st International Conference on Computer Design
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Rescue: A Microarchitecture for Testability and Defect Tolerance
Proceedings of the 32nd annual international symposium on Computer Architecture
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
The Topological Properties and Network Embedding of RP(k)
PDCAT '05 Proceedings of the Sixth International Conference on Parallel and Distributed Computing Applications and Technologies
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An abacus turn model for time/space-efficient reconfigurable routing
Proceedings of the 38th annual international symposium on Computer architecture
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
RISO: relaxed network-on-chip isolation for cloud processors
Proceedings of the 50th Annual Design Automation Conference
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.