Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Graph Theory With Applications
Graph Theory With Applications
Increased Throughput for the Testing and Repair of RAMs with Redundancy
IEEE Transactions on Computers
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Repair of Memory Arrays by Cutting
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testability strategy of the Alpha AXP 21164 microprocessor
ITC'94 Proceedings of the 1994 international conference on Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
Improved FPT algorithms for rectilinear k-links spanning path
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
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The issue of yield degradation due to physical failures in large memory and processor arrays is of significant importance to semiconductor manufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is by incorporating spare rows and columns in the die or wafer which can be programmed into the array. This paper addresses the issue of computer-aided design approaches to optimal reconfiguration of such arrays. The paper presents the first formal analysis of the problem. The complexity of optimal reconfiguration is shown to be NP-complete for rectangular arrays utilizing spare rows and columns. In contrast to previously proposed exhaustive search and greedy algorithms, this paper develops a heuristic branch and bound approach based on the complexity analysis, which allows for flexible and highly efficient reconfiguration. Initial screening is performed by a bipartite graph matching algorithm.