Efficient spare allocation in reconfigurable arrays
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Testability access of the high speed test features in the Alpha 21264 microprocessor
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
Testability strategy of the Alpha AXP 21164 microprocessor
ITC'94 Proceedings of the 1994 international conference on Test
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Memory Built-In Self-Repair using redundant words
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Balanced dual-stage repair for dependable embedded memory cores
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
Yield improvement and power aware low cost memory chips
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modified essential spare pivoting algorithm for embedded memories with global block-based redundancy
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An innovative self-test and self-repairtechnique supports Built-in Self-test andBuilt-in Self-repair of large embedded RAMarrays with spare rows and columns. Thetechnique generates and analyzes the requiredfailure bitmap information on the fly duringself-test and then automatically repairs andverifies the repaired RAM arrays.