Flash Memories
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories
Journal of Electronic Testing: Theory and Applications
Test cost reduction by at-speed BISR for embedded DRAMs
Proceedings of the IEEE International Test Conference 2001
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Flash Memory Built-In Self-Test Using March-Like Algorithms
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Method to Caculate Redundancy Coverage for FLASH Memory
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Built-In Self-Repair Scheme for NOR-Type Flash Memory
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing content-addressable memories using functional fault models and march-like algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
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The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for NOR flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of NOR flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting NOR flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories.