Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Memory Built-In Self-Repair using redundant words
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Repair of Large Embedded DRAMs: Part 1
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test cost reduction by at-speed BISR for embedded DRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Repair of Large Embedded DRAMs: part 2
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Balanced dual-stage repair for dependable embedded memory cores
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
SoC Design and Test Considerations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EOF: efficient built-in redundancy analysis methodology with optimal repair rate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Constraint bipartite vertex cover: simpler exact algorithms and implementations
Journal of Combinatorial Optimization
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new practical built-in self-repair analyzer algorithm forembedded DRAMs (e-DRAM) achieves 100% detectionability of the repairable chips with 1% area penalty of thetarget 32Mb embedded DRAM by 4 parallel analyzers. Itworks at as fast as 500MHz, well beyond targeted e-DRAMs' maximum operation speed around 200MHz+.