Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Mapping and Repairing Embedded-Memory Defects
IEEE Design & Test
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SRAM yield estimation in the early stage of the design cycle
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Industrial Evaluation of DRAM SIMM Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Automatic Generation of Diagnostic March Tests
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
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Systems-on-Chips often contain a large amount of embedded memory. In order to obtain sufficiently high yield, efficient diagnosis and repair facilities are needed for the memories. A novel and efficient approach for collecting complete failure data during on-chip memory testing is proposed that can be combined with a row/column reconfiguration algorithm for complete on-chip memory repair. A sequence of diagnostic tests of linear order is utilized that detects and localizes all cells involved in single-cell faults and two-cell coupling faults, such as idempotent coupling faults, and provides this information to on-chip circuitry for memory repair. Failure data are collected at the operating speed of the memory-under-test so that tests can be applied at speed. The data acquisition circuitry evaluates the test results and classifies faults as column failures, coupling faults, or single-cell faults for near-optimal allocation of spare resources. The proposed test and data acquisition algorithm can be realized as compact Built-In Self-Test (BIST) circuitry using standard design libraries.