Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
A 256Meg SDRAM BIST for Disturb Test Application
Proceedings of the IEEE International Test Conference
Design of Cache Test Hardware on the HP PA8500
Proceedings of the IEEE International Test Conference
Hardware Compression Speeds on Bitmap Fail Display
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Compressed Bit Fail Maps for Memory Fail Pattern Classification
Journal of Electronic Testing: Theory and Applications
Compressed Bit Fail Maps for Memory Fail Pattern Classification
ETW '00 Proceedings of the IEEE European Test Workshop
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Memories are often used as a semiconductormanufacturing process monitoring vehicle. This paperdescribes a new memory Built-In Self-Test (BIST) methodthat is used to monitor the semiconductor manufacturingprocess. For this purpose, this BIST method has the abilitynot only to generate a pass/fail verdict for the testedmemory, but also to report additional information to beable to narrow down the type and the location of thefailure mode that is causing the tested memory to fail.Also, it offers test algorithm flexibility. The described BISTmethod has successfully been implemented in a dedicatedprocess monitoring chip that is now being used in largequantities.