Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
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The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.