An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Partitioned register file for TTAs
Proceedings of the 28th annual international symposium on Microarchitecture
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
IEEE Transactions on Computers
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
A Bist Scheme for Non-Volatile Memories
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Cost and benefit models for logic and memory BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Dynamic Power Supply Current Testing of CMOS SRAMs
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
Simulation-based test algorithm generation and port scheduling for multi-port memories
Proceedings of the 38th annual Design Automation Conference
An on-chip march pattern generator for testing embedded memory cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation and compaction of March Tests for memory arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IDDQ Testing of Opens in CMOS SRAMs
Journal of Electronic Testing: Theory and Applications
Fault Models and Test Procedures for Flash Memory Disturbances
Journal of Electronic Testing: Theory and Applications
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
Journal of Electronic Testing: Theory and Applications
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
IEEE Design & Test
Industrial BIST of Embedded RAMs
IEEE Design & Test
Mapping and Repairing Embedded-Memory Defects
IEEE Design & Test
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test
Design of Cache Test Hardware on the HP PA8500
IEEE Design & Test
Fault Models and Tests for a 2-Bit-per-Cell MLDRAM
IEEE Design & Test
Online and Offline BIST in IP-Core Design
IEEE Design & Test
IEEE Design & Test
DFT and BIST of a Multichip Module for High-Energy Physics Experiments
IEEE Design & Test
Transient Fault Tolerance in Digital Systems
IEEE Micro
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories
Journal of Electronic Testing: Theory and Applications
Testing and Characterization of SDRAMs
IEEE Design & Test
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Quad DCVS dynamic logic fault modeling and testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A highly testable and diagnosable fabrication process test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing a multichip package for a consumer communications application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
How we test Siemens Embedded DRAM Cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for generating optimal March tests for memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Novel Built-In Self-Repair Approach for Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Online Self-Repair of FIR Filters
IEEE Design & Test
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Functional test for shifting-type FIFOs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
RAM Testing Algorithm for Detection Linked Coupling Faults
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Test and Testability Techniques for Open Defects in RAM Address Decoders
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Towards a Uniform Notation for Memory Tests
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fault Models and Test Strategies for a Two-Bit per Cell DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Address Decoder Faults and their Tests for Two-Port Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Converting March Tests for Bit-Oriented Memories Into Tests for Word-Oriented Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
DRAM Fault Modeling and Test Pattern Design
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Verification of CAM Tests for Input Stuck-at Faults
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Functional Testing of Content-Addressable Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Assessing SRAM test coverage for sub-micron CMOS technologies
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Disturb Neighborhood Pattern Sensitive Fault
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
18.1 A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
1.1 Designing a Testable System on a Chip
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
6.1 IDDQ Testing of Opens in CMOS SRAMs
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Bare Die Test Methodology
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Self Test Architecture for Testing Complex Memory Structures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Industrial Evaluation of DRAM SIMM Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Methodology for the McKinley Processor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Simulation Based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Shadow Write and Read For At-Speed BIST Of TDM SRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
GRAAL: a Tool for Highly Dependable SRAMs Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
WEAK WRITE TEST MODE: AN SRAM CELL STABILITY DESIGN FOR TEST TECHNIQUE
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A 256Meg SDRAM BIST for Disturb Test Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Method of Embedded Memory Access Time Measurement
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Recent developments in dram testing
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Built in self testing for detection of coupling faults in semiconductor memories
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Methods for memory test time reduction
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
A true testprocessor-per-pin algorithmic pattern generator
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Testing strategies for networks on chip
Networks on chip
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Practical Scan Test Generation and Application for Embedded FIFOs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An On-Line BISTed SRAM IP Core
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing An MCM For High-Energy Physics Experiments: A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Nondestructive RAM Testing by Analyzing the Output Data for Symmetry
Automation and Remote Control
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Soft Faults and the Importance of Stresses in Memory Testing
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Reducing Embedded SRAM Test Time under Redundancy Constraints
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories
Journal of Electronic Testing: Theory and Applications
Memory Fault Modeling Trends: A Case Study
Journal of Electronic Testing: Theory and Applications
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Sorting and searching in the presence of memory faults (without redundancy)
STOC '04 Proceedings of the thirty-sixth annual ACM symposium on Theory of computing
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SRAM delay fault modeling and test algorithm development
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
Consequences of RAM Bitline Twisting for Test Coverage
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Industrial Evaluation of DRAM Tests
IEEE Design & Test
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
New Schemes for Self-Testing RAM
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Reliability assessment in embryonics inspired by fault-tolerant quantum computation
Proceedings of the 2nd conference on Computing frontiers
Multiple-level concatenated coding in embryonics: a dependability analysis
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Journal of Electronic Testing: Theory and Applications
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Yield Enhancement Methodology for CMOS Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Minimizing test power in SRAM through reduction of pre-charge activity
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Crosstalk Induced Fault Analysis and Test in DRAMs
Journal of Electronic Testing: Theory and Applications
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
Formal Methods in System Design
Opens and Delay Faults in CMOS RAM Address Decoders
IEEE Transactions on Computers
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories
Journal of Electronic Testing: Theory and Applications
The repeated nondestructive march tests with variable address sequences
Automation and Remote Control
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
Journal of Electronic Testing: Theory and Applications
A sophisticated memory test engine for LCD display drivers
Proceedings of the conference on Design, automation and test in Europe
The price of resiliency: a case study on sorting with memory faults
ESA'06 Proceedings of the 14th conference on Annual European Symposium - Volume 14
Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
Journal of Electronic Testing: Theory and Applications
Design-for-test techniques for opens in undetected branches in CMOS latches and flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
Localized random access scan: towards low area and routing overhead
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Extending boundary-scan to perform a memory built-in self-test
ICC'05 Proceedings of the 9th International Conference on Circuits
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A simple diagnostic method for memory testing
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
A design-for-diagnosis technique for SRAM write drivers
Proceedings of the conference on Design, automation and test in Europe
A new march sequence to fit DDR SDRAM test in burst mode
Proceedings of the 21st annual symposium on Integrated circuits and system design
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fault models for embedded-DRAM macros
Proceedings of the 46th Annual Design Automation Conference
BIST design optimization for large-scale embedded memory cores
Proceedings of the 2009 International Conference on Computer-Aided Design
Radioport: a radio network for monitoring and diagnosing computer systems
Radioport: a radio network for monitoring and diagnosing computer systems
Analysis of resistive-open defects in SRAM sense amplifiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
Genetic algorithm for test pattern generator design
Applied Intelligence
Memory testing with a RISC microcontroller
Proceedings of the Conference on Design, Automation and Test in Europe
A new design-for-test technique for SRAM core-cell stability faults
Proceedings of the Conference on Design, Automation and Test in Europe
Testing comparison and delay faults of TCAMs with asymmetric cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in system test and fault location
ITC'94 Proceedings of the 1994 international conference on Test
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
The powerPC 603TM microprocessor: an array built-in self test mechanism
ITC'94 Proceedings of the 1994 international conference on Test
Efficient O(√n ) BIST algorithms for DDNPS faults in dual port memories
ITC'94 Proceedings of the 1994 international conference on Test
Transparent memory testing for pattern sensitive faults
ITC'94 Proceedings of the 1994 international conference on Test
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient cache design using variable-strength error-correcting codes
Proceedings of the 38th annual international symposium on Computer architecture
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
Designing reliable algorithms in unreliable memories
ESA'05 Proceedings of the 13th annual European conference on Algorithms
Experimental study of resilient algorithms and data structures
SEA'10 Proceedings of the 9th international conference on Experimental Algorithms
Resilient algorithms and data structures
CIAC'10 Proceedings of the 7th international conference on Algorithms and Complexity
Designing reliable algorithms in unreliable memories
Computer Science Review
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
Journal of Electronic Testing: Theory and Applications
Priority queues resilient to memory faults
WADS'07 Proceedings of the 10th international conference on Algorithms and Data Structures
Automation and Remote Control
Test solution for data retention faults in low-power SRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
Proceedings of the 40th Annual International Symposium on Computer Architecture
Modeling and testing of interference faults in the nano NAND flash memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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