Analysis of resistive-open defects in SRAM sense amplifiers

Authors:
Alexandre Ney;Patrick Girard;Serge Pravossoudovitch;Arnaud Virazel;Magali Bastian
Affiliations:
Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université de Montpellier II, CNRS, Montpellier Cedex, France;Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université de Montpellier II, CNRS, Montpellier Cedex, France;Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université de Montpellier II, CNRS, Montpellier Cedex, France;Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université de Montpellier II, CNRS, Montpellier Cedex, France;Infineon Technologies, Sophia-Antipolis, France
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 10
Cited 1

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
Open Defects in CMOS RAM Address Decoders

IEEE Design & Test
Integration of Non-Classical Faults in Standard March Tests

MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Importance of Dynamic Faults for New SRAM Technologies

ETW '03 Proceedings of the 8th IEEE European Test Workshop
March iC-: An Improved Version of March C- for ADOFs Detection

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Journal of Electronic Testing: Theory and Applications
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

ETS '07 Proceedings of the 12th IEEE European Test Symposium
Slow write driver faults in 65nm SRAM technology: analysis and March test solution

Proceedings of the conference on Design, automation and test in Europe
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Journal of Electronic Testing: Theory and Applications

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present an exhaustive analysis of resistive-open defects in sense amplifiers of static random access memory designed with a 65 nm technology. We show that some resistive-open defects may lead to a new type of dynamic behavior that has never been experienced in the past. It is modeled by dynamic two-cell incorrect read faults of two different types. Such fault models represent failures in the sense amplifier, which prevent it from performing any read operations (in case of type 1 [1]) or only a single type of read operation (in case of type 2). Results of electrical simulations are presented to provide a complete understanding of such a faulty behavior and possible March test solutions are proposed to detect all d2cIRFs.