Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and Testability Techniques for Open Defects in RAM Address Decoders
EDTC '96 Proceedings of the 1996 European conference on Design and Test
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
IEEE Transactions on Computers
IEEE Transactions on Computers
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March iC-: An Improved Version of March C- for ADOFs Detection
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Proceedings of the 42nd annual Design Automation Conference
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Journal of Electronic Testing: Theory and Applications
Minimizing test power in SRAM through reduction of pre-charge activity
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
Slow write driver faults in 65nm SRAM technology: analysis and March test solution
Proceedings of the conference on Design, automation and test in Europe
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
Journal of Electronic Testing: Theory and Applications
Analysis of resistive-open defects in SRAM sense amplifiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
Genetic defect based march test generation for SRAM
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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