Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution
ATS '04 Proceedings of the 13th Asian Test Symposium
Framework for Fault Analysis and Test Generation in DRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Opens and Delay Faults in CMOS RAM Address Decoders
IEEE Transactions on Computers
March Test Generation Revealed
IEEE Transactions on Computers
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The continuos shrinking of semiconductor's nodes makes semiconductor memories increasingly prone to electrical defects tightly related to the internal structure of the memory. Exploring the effect of fabrication defects in future technologies, and identifying new classes of functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure exploiting a dedicated genetic algorithm.