Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Embedding infrastructure IP for SOC yield improvement
Proceedings of the 39th annual Design Automation Conference
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
IEEE Design & Test
Generating March Tests Automatically
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Simulation-Based Test Algorithm Generation for Random Access Memories
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Automatic Generation of Diagnostic March Tests
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Genetic defect based march test generation for SRAM
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
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A memory failure analysis framework is developed-the FailureAnalyzer for MEmories (FAME). The FAME integrates the MemoryError Catch and Analysis (MECA) system and the Memory Defect Diagnostics(MDD) system. The fault-type based diagnostics approachused by MECA can improve the efficiency of the test and diagnosticalgorithms. The fault-pattern based diagnostics approach used byMDD further improves the defect identification capability. The FAMEalso comes with a powerful viewer for inspecting the failure patternsand fault patterns. It provides an easy way to narrow down the potentialcause of failures and identify possible defects more accuratelyduring the memory product development and yield ramp-up stage.An experiment has been done on an industrial case, demonstratingvery accurate results in a much shorter time as compared with theconventional way.