Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
Optimizing Memory Tests by Analyzing Defect Coverage
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Integrated Diagnostics for Embedded Memory Built-in Self Test on PowerPCTM Devices
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement
Journal of Electronic Testing: Theory and Applications
Yield Enhancement Methodology for CMOS Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Analyzing bitmap results can provide insight into physical failure mechanisms normally acquired only through the complex, time-consuming, and expensive process of failure analysis.