Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis

Using Electrical Bitmap Results from Embedded Memory to Enhance Yield

IEEE Design & Test

Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield

IEEE Design & Test

Challenges in Embedded Memory Design and Test

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

ProTaR: an infrastructure IP for repairing RAMs in system-on-chips

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient memory repair using cache-based redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems