Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test cost reduction by at-speed BISR for embedded DRAMs
Proceedings of the IEEE International Test Conference 2001
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Approach for Evaluation of Redunancy Analysis Algorithms
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fail Pattern Identification for Memory Built-In Self-Repair
ATS '04 Proceedings of the 13th Asian Test Symposium
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EOF: efficient built-in redundancy analysis methodology with optimal repair rate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories--two 8 K × 64 bit SRAMs, one 4 K × 16 bit SRAM, and one 2 K × 32 bit SRAM--based on TSMC 0.18-µm standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.