Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Strategy of the ALPHA AXP 21164 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Online diagnosis of hard faults in microprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for test and reliability in ultimate CMOS
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
In modern SoCs, embedded memories occupythe largest part of the chip area and include an evenlarger amount of active devices. As memories aredesigned very tightly to the limits of the technology theyare more prone to failures than logic. Thus, theyconcentrate the large majority of defects and affect circuityield dramatically. Thus, Built-In Self-Repair is gainingsignificant importance. This work presents a dynamicmemory built-in self-repair schemer acting on the data-bitlevel. It allows reducing the size of the repairable units,or in other words, it allows using a single spare unit forrepairing faults affecting several regular units. As aconsequence, it repairs multiple faults by means of lowhardware cost.