Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Strategy of the ALPHA AXP 21164 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays
IFM '09 Proceedings of the 7th International Conference on Integrated Formal Methods
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
Design for test and reliability in ultimate CMOS
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Memory Reliability Improvement Based on Maximized Error-Correcting Codes
Journal of Electronic Testing: Theory and Applications
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Memory Built In Self Repair (BISR) is gainingimportance since several years. Because defectdensities are increasing with submicron scaling, moreadvanced solutions may be required for memories tobe produced with the upcoming nanometric CMOSprocess generations. This problem will be exacerbatedwith nanotechnologies, where defect densities arepredicted to reach levels that are several orders ofmagnitude higher than in current CMOS technologies.For such defect densities, traditional memory repair isnot adequate. This work presents a diversified repairapproach merging ECC codes and self-repair, forrepairing memories affected by high defect densities.The approach was validated by means of statisticalfault injection simulations considering defect densitiesas high as 3*10{-2} % (3% of cells are defective). Theobtained results show that the approach providesclose to 100% memory yield, by means of reasonablehardware cost, for technologies of very poor quality.Thus, the extreme defect densities that many authorspredict for nanotechnologies do not represent a show-stopper,at least as concerning memories.