Mechanizing programming logics in higher order logic
Current trends in hardware verification and automated theorem proving
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Introduction to Monte Carlo methods
Proceedings of the NATO Advanced Study Institute on Learning in graphical models
Model-Checking Algorithms for Continuous-Time Markov Chains
IEEE Transactions on Software Engineering
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
VESTA: A Statistical Model-checker and Analyzer for Probabilistic Systems
QEST '05 Proceedings of the Second International Conference on the Quantitative Evaluation of Systems
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
Formalization of Continuous Probability Distributions
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
Formal probabilistic analysis using theorem proving
Formal probabilistic analysis using theorem proving
Quantitative Analysis With the Probabilistic Model Checker PRISM
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of expectation properties for discrete random variables in HOL
TPHOLs'07 Proceedings of the 20th international conference on Theorem proving in higher order logics
Formal Reasoning about Expectation Properties for Continuous Random Variables
FM '09 Proceedings of the 2nd World Congress on Formal Methods
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Reconfigurable memory arrays with spare rows and columns are quite frequently used as reliable data storage components in present age System-on-Chips (SoCs). The spare memory rows and columns can be utilized to automatically replace rows or columns that are found to contain a cell fault after fabrication. One of the biggest SoC design challenges is to estimate, prior to the actual fabrication process, the right number of these spare rows and spare columns for meeting the reliability specifications. Traditionally, computer simulation techniques are used to perform probabilistic analysis of reconfigurable memory arrays but they provide inaccurate results. To ensure accurate analysis and thus more reliable SoC designs, we propose, in this paper, a probabilistic theorem proving approach in the domain of reconfigurable memory array analysis. We present a higher-order-logic stuck-at fault model for reconfigurable memory arrays, based on which, we illustrate the formal verification of some key statistical properties related to the number of stuck-at faults and the repairability condition.