An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover
MFCS '99 Proceedings of the 24th International Symposium on Mathematical Foundations of Computer Science
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
New Architecture and Algorithms for Degradable VLSI/WSI Arrays
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Some Prospects for Efficient Fixed Parameter Algorithms
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures.
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Run-time Reconfiguration Algorithm for VLSI Arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
Yield improvement and power aware low cost memory chips
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
Constraint Bipartite Vertex Cover Simpler Exact Algorithms and Implementations
FAW '08 Proceedings of the 2nd annual international workshop on Frontiers in Algorithmics
Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays
IFM '09 Proceedings of the 7th International Conference on Integrated Formal Methods
Redundancy analysis simulation in semiconductor manufacturing for yield improvement
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
An exact algorithm based on chain implication for the Min-CVCB problem
COCOA'07 Proceedings of the 1st international conference on Combinatorial optimization and applications
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EOF: efficient built-in redundancy analysis methodology with optimal repair rate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic techniques for yield enhancement of field programmable logic arrays
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Exact exponential-time algorithms for finding bicliques
Information Processing Letters
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability of VLSI linear arrays with redundant links
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
On the repair of memory cells with spare rows and columns for yield improvement
AsiaSim'04 Proceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications
Constraint bipartite vertex cover: simpler exact algorithms and implementations
Journal of Combinatorial Optimization
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Yield degradation from physical failures in large memories and processor arrays is of significant concern to semiconductormanufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is to incorporatespare rows and columns in the die or wafer. These spare rows and columns can then be programmed into the array. The authorsdiscuss the use of CAD approaches to reconfigure such arrays. The complexity of optimal reconfiguration is shown to be NP-complete.The authors present two algorithms for spare allocation that are based on graph-theoretic analysis. The first uses a branch-and-boundapproach with early screening based on bipartite graph matching. The second is an efficient polynomial time-approximationalgorithm. In contrast to existing greedy and exhaustive search algorithms, these algorithms provide highly efficient andflexible reconfiguration analysis.