On the repair of redundant RAMs
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Increased Throughput for the Testing and Repair of RAMs with Redundancy
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Hypergraph Coloring and Reconfigured RAM Testing
IEEE Transactions on Computers
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
A Novel Built-In Self-Repair Approach for Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Memory Built-In Self-Repair using redundant words
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
Journal of Electronic Testing: Theory and Applications
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Memory Defect Tolerance Architectures for Nanotechnologies
Journal of Electronic Testing: Theory and Applications
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
Yield improvement and power aware low cost memory chips
Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
Proceedings of the 13th international symposium on Low power electronics and design
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Modified essential spare pivoting algorithm for embedded memories with global block-based redundancy
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM leakage reduction by row/column redundancy under random within-die delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As the density of embedded memory increases,manufacturing yields of integrated circuits canreach unacceptable limits. Normal memory testingoperations require Built-In Self Test (BIST)to effectively deal with problems such as limitedaccess and "at speed" testing. In this paper wedescribe a novel methodology that extends theBIST concept to diagnosis and repair utilizingredundant components. We describe an applicationusing redundant columns and accompanyingalgorithms. It allows for the autonomousrepair of defective circuitry without externalstimulus (e.g. laser repair). The method has beenimplemented with negligible timing penaltiesand reasonable area overhead.