Integrating Scan into Hierarchical Synthesis Methodologies
Proceedings of the IEEE International Test Conference on Test and Design Validity
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Embedded Self Repair by Transistor and Gate Level Reconfiguration
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
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We propose a yield improvement methodology which repairs a faulty chip due to logic defect by using a repairable scan flip-flop (R-SFF). Our methodology improves area penalty, which is a large issue for logic repair technology in actual products, by using repair grouping and a redundant cell insertion algorithm and by pushing the design rule for the repairable area of R-SFF. Additionally, compared with the conventional method, we reduce the number of wire connections around redundant cells by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces the total area penalty caused by the logic redundant repair to 3.6% and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[1/cm^2]. Furthermore, we propose the strategy to repair the in-field failures due to latent defect for the chip whose repair function had not been used in the shipment test.