Integrating Scan into Hierarchical Synthesis Methodologies

A new approach to scan chain reordering using physical design information

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Test-model based hierarchical DFT synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Scan chain clustering for test power reduction

Proceedings of the 45th annual Design Automation Conference

Test strategies for low power devices

Proceedings of the conference on Design, automation and test in Europe

A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule

ACM Transactions on Design Automation of Electronic Systems (TODAES)