Introducing Core-Based System Design
IEEE Design & Test
Integrating Scan into Hierarchical Synthesis Methodologies
Proceedings of the IEEE International Test Conference on Test and Design Validity
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CTL the language for describing core-based test
Proceedings of the IEEE International Test Conference 2001
A Simulation-Based Protocol-Driven Scan-Test-Design Rule Checker
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
ATS '00 Proceedings of the 9th Asian Test Symposium
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With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution, involving the introduction of test models in a traditional DFT synthesis flow, that we term Hierarchical DFT Synthesis (HDS). We discuss the use of Core Test Language (CTL) based test models combined with physical and timing models to provide a complete flow for chip-level DFT. In doing so we address some challenges the new flow presents such as Design Rule Checking (DRC), DFT architecting and optimization. We describe methods to overcome these challenges thereby presenting a new methodology to handle complex next generation designs.