Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Integrating Scan into Hierarchical Synthesis Methodologies
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Layout Driven Design for Testability Technique for MOS VLSI Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test-model based hierarchical DFT synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
Routing-aware scan chain ordering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A routability constrained scan chain ordering technique for test power reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synthesis-for-testability watermarking for field authenticatioil of VLSI intellectual property
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Scan chain reordering based on physical design informationhelps in reducing routing bottleneck and in minimizingdesign constraint violations. This paper proposesintegrating this capability into synthesis-based design reoptimization.It describes the benefits of such an approach, thedesign synthesis context, presents new ordering conceptsand concludes with results on real designs.