ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Integrating DFT in the Physical Synthesis Flow
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
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Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.