Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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We propose a linear-time algorithm for post-placement scan chain optimization tha works efficiently on large designs and that allows user-specified tradeoffs between runtime and solution quality.This algorithm is also efficiently applied on scan chain partitioning.