Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
Introduction to Linear Optimization
Introduction to Linear Optimization
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhancing Delay Fault Coverage through Low Power Segmented Scan
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this paper, we propose minimum-violations partitioning (MVP), a scan-cell clustering method that can support multiple capture cycles in delay testing without increasing test-data volume. This method is based on an integer linear programming model and it can cluster the scan flip-flops into balanced parts with minimum capture violations. Based on this approach, hierarchical partitioning is proposed to make the partitioning method routingaware. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits demonstrate the effectiveness of our method.