A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
On Using Machine Learning for Logic BIST
Proceedings of the IEEE International Test Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Low Power BIST by Filtering Non-Detecting Vectors
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Power Dissipation During Testing: Should We Worry About it?
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Journal of Systems Architecture: the EUROMICRO Journal
Scan Array Solution for Testing Power and Testing Time
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A low power consumption BIST testing technology based on heavy input
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
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Power consumption of digital systems may increasesignificantly during testing. In this paper, we propose anovel low power/energy Built-In Self Test (BIST) strategybased on circuit partitioning. The strategy consists inpartitioning the original circuit into structural subcircuitsso that each subcircuit can be successively tested throughdifferent BIST sessions. In partitioning the circuit andplanning the test session, the switching activity in a timeinterval (i.e. the average power) as well as the peak powerconsumption are minimized. Moreover, the total energyconsumption during BIST is also reduced since the testlength required to test the subcircuits is not so far from thetest length for the original circuit. The proposed strategycan be applied to either test-per-scan or test-per-clockBIST schemes by slightly modifying conventional TPGstructures as illustrated in this paper. Results on ISCAScircuits show that average power reduction of up to 62%,peak power reduction of up to 57%, and energy reductionof up to 82% can be achieved at a very low area cost interms of area overhead and with almost no penalty on thecircuit timing.