DS-LFSR: A New BIST TPG for Low Heat Dissipation

Low Power BIST by Filtering Non-Detecting Vectors

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Minimized Power Consumption for Scan-Based BIST

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

Journal of Electronic Testing: Theory and Applications

Power-/Energy Efficient BIST Schemes for Processor Data Paths

IEEE Design & Test

Survey of Low-Power Testing of VLSI Circuits

IEEE Design & Test

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Journal of Systems Architecture: the EUROMICRO Journal

Low-Energy BIST Design for Scan-based Logic Circuits

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

19.3 Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

A Test Vector Inhibiting Technique for Low Energy BIST Design

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power Testing of VLSI Circuits: Problems and Solutions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Low Power BIST for Wallace Tree-Based Fast Multipliers

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Peak Power Reduction in Low Power BIST

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A Queueing System with Inverse Discipline, Two Types of Customers, and Markov Input Flow

Automation and Remote Control

Low-power weighted pseudo-random BIST using special scan cells

Proceedings of the 14th ACM Great Lakes symposium on VLSI

A routability constrained scan chain ordering technique for test power reduction

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

A Gated Clock Scheme for Low Power Testing of Logic Cores

Journal of Electronic Testing: Theory and Applications

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

Journal of Electronic Testing: Theory and Applications

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

DFT and minimum leakage pattern generation for static power reduction during test and burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Suitability of various low-power testing techniques for IP core-based SoC: a survey

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal