IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BUILT-IN RESEEDING FOR SERIAL BIST
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Low Power Pseudo-Random BIST Technique
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
Survey of Test Vector Compression Techniques
IEEE Design & Test
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel x-ploiting strategy for improving performance of test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Electrical Engineering
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOCRATES: a highly efficient automatic test pattern generation system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple distributions for biased random test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0's and 1's and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.