An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Low Power/Energy BIST Scheme for Datapaths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Trends in SLI design and their effect on test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Embedded X86 Testing Methodology
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Analysis of Powe Reduction Techniques in Scan Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Reducing Average and Peak Test Power Through Scan Chain Modification
Journal of Electronic Testing: Theory and Applications
A Queueing System with Inverse Discipline, Two Types of Customers, and Markov Input Flow
Automation and Remote Control
Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method
Automation and Remote Control
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing
Journal of Electronic Testing: Theory and Applications
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Journal of Electronic Testing: Theory and Applications
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Graph theoretic approach for scan cell reordering to minimize peak shift power
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Gating internal nodes to reduce power during scan shift
Proceedings of the 20th symposium on Great lakes symposium on VLSI
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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Scan architectures are commonly used to testdigital circuitry in integrated circuits. This paperdescribes a method of adapting conventional scanarchitectures such that they operate in a low powermode during test. The adapted scan architecturesmaintain the test times of the pre-adapted scanarchitectures. Also, the adaptation occurs in a manner that enables the test patterns of the preadapted scan architecture to be directly reusable in the adapted scan architecture.