Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

Authors:
Wang-Dauh Tseng
Affiliations:
Department of Computer Science & Engineering, Yuan Ze University, Chung-li, Republic of China 32026
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2007

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Abstract

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.