Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Rescue: A Microarchitecture for Testability and Defect Tolerance
Proceedings of the 32nd annual international symposium on Computer Architecture
Journal of Electronic Testing: Theory and Applications
Accurate Diagnosis of Multiple Faults
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
At-Speed Logic BIST Architecture for Multi-Clock Designs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Debugging sequential circuits using Boolean satisfiability
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Opens and Delay Faults in CMOS RAM Address Decoders
IEEE Transactions on Computers
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing
Journal of Electronic Testing: Theory and Applications
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
Journal of Electronic Testing: Theory and Applications
Reducing verification overhead with RTL slicing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
Journal of Electronic Testing: Theory and Applications
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
Towards design for self-healing
Fourth international workshop on Software quality assurance: in conjunction with the 6th ESEC/FSE joint meeting
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective realization of on-chip fault-tolerance utilizing BIST resources
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Journal of Electronic Testing: Theory and Applications
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Self checking systolic FIFO stack
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Automatic test generation for combinational threshold logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Consistency-based characterization for IC Trojan detection
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complex oscillation-based test and its application to analog filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Hazard-based detection conditions for improved transition path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of multiple arbitrary faults with mask and reinforcement effect
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient cache design using variable-strength error-correcting codes
Proceedings of the 38th annual international symposium on Computer architecture
Test-case generation for embedded simulink via formal concept analysis
Proceedings of the 48th Design Automation Conference
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
Proceedings of the 40th Annual International Symposium on Computer Architecture
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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From the Publisher:As the complexity of modern digital systems increases, so does the need for ever more rigorous testing at all levels, from individual chips up to complete system architectures. This book is the most comprehensive introduction available to the range of techniques and tools used in digital testing. It covers every key topic, including fault simulation, CMOS testing, design for testability, and built-in self test. Aimed at graduate students of electrical and computer engineering, the book is also the most up-to-date reference on the market for practicing engineers.