Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains

Authors:
Laung-Terng Wang;Xiaoqing Wen;Shianling Wu;Hiroshi Furukawa;Hao-Jan Chao;Boryau Sheu;Jianghao Guo;Wen-Ben Jone
Affiliations:
SynTest Techn., Inc., Sunnyvale, CA and the Graduate Inst. of Electronics Eng., Natl. Taiwan Univ., Taipei, and Dept. of Creative Inf., Kyushu Inst. of Techn., Iizuka, Fukuoka, Japan and Sch. of S ...;Department of Creative Informatics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;SynTest Technologies, Inc., Princeton Junction, NJ;Department of Creation Informatics, Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan and NEC Micro Systems, Ltd., Kumamoto, Japan;SynTest Technologies, Inc., Hsinchu, Taiwan;Sigma Designs, Milpitas, CA;Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH;Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.