VirtualScan: A New Compressed Scan Technology for Test Cost Reduction

Authors:
Laung-Terng Wang;Khader S. Abdel-Hafez;Shianling Wu;Xiaoqing Wen;Hiroshi Furukawa;Fei-Sheng Hsu;Shyh-Horng Lin;Sen-Wei Tsai
Affiliations:
SynTest Technologies, Inc., Sunnyvale , CA;SynTest Technologies, Inc., Sunnyvale , CA;SynTest Technologies, Inc., Sunnyvale , CA;Kyushu Institute of Technology, Japan;NEC Micro Systems, Ltd., Japan;SynTest Technologies, Inc., Taiwan;SynTest Technologies, Inc., Taiwan;SynTest Technologies, Inc., Taiwan
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

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Abstract

This paper describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.