Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Parity-Based Output Compaction for Core-Based SOCs
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Compactor Independent Direct Diagnosis
ATS '04 Proceedings of the 13th Asian Test Symposium
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Value-Added Defect Testing Techniques
IEEE Design & Test
X-Tolerant Test Response Compaction
IEEE Design & Test
An Economic Analysis and ROI Model for Nanometer Test
ITC '04 Proceedings of the International Test Conference on International Test Conference
Realizing High Test Quality Goals with Smart Test Resource Usage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Trends in Testing Integrated Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor
ATS '06 Proceedings of the 15th Asian Test Symposium
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As today's process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to `X' tolerance and aliasing.