Test Method Evaluation Experiments & Data

Authors:
Phil Nigh;Anne Gattiker
Affiliations:
-;-
Venue:
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Year:
2000

Citing 31
Cited 20

Identifying defects in deep-submicron CMOS ICs

IEEE Spectrum
Microprocessor IDDQ Testing: A Case Study

IEEE Design & Test
Defect Classes - An Overdue Paradigm for CMOS IC

Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An Experimental Chip to Evaluate Test Techniques: Experiment Results

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On the Effect of ISSQ Testing in Reducing Early Failure Rate

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data

Proceedings of the IEEE International Test Conference
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment

Proceedings of the IEEE International Test Conference
Signature Analysis for IC Diagnosis and Failure Analysis

Proceedings of the IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Process-tolerant test with energy consumption ratio

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Toward understanding "Iddq-only" fails

ITC '98 Proceedings of the 1998 IEEE International Test Conference
iDD Pulse Response Testing of Analog and Digital CMOS Circuits

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Very-Low-Voltage Testing for Weak CMOS Logic ICs

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
IDDQ Defect Detection in Deep Submicron CMOS ICs

ATS '98 Proceedings of the 7th Asian Test Symposium
Iddq Testing for High Performance CMOS - The Next Ten Years

EDTC '96 Proceedings of the 1996 European conference on Design and Test
Current signatures [VLSI circuit testing]

VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Bridges in sequential CMOS circuits: current-voltage signature

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Cold Delay Defect Screening

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Testing for Tunneling Opens

ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Current Signatures: Application

ITC '97 Proceedings of the 1997 IEEE International Test Conference
The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination

IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
SHOrt Voltage Elevation (SHOVE) Testing

IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
A Comprehensive Wafer Oriented Test Evaluation (Wote) Scheme For The Iddq Testing Of Deep Sub-Micron Technologies

IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing

ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Performance Comparison of VLV, ULV, and ECR Tests

Journal of Electronic Testing: Theory and Applications
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

Journal of Electronic Testing: Theory and Applications
Replacing IDDQ Testing: With Variance Reduction

Journal of Electronic Testing: Theory and Applications
Multiple-Output Propagation Transition Fault Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Practical Application of Energy Consumption Ratio Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology

IEEE Design & Test
Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs

IEEE Design & Test
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings

IEEE Design & Test
On New Current Signatures and Adaptive Test Technique Combination

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Detection of multiple transitions in delay fault test of SPARC64 microprocessor

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Evaluation of the statistical delay quality model

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Via Distribution Model for Yield Estimation

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Scan Test Response Compaction Combined with Diagnosis Capabilities

Journal of Electronic Testing: Theory and Applications
Small-delay defect detection in the presence of process variations

Microelectronics Journal
Globally optimized robust systems to overcome scaled CMOS reliability challenges

Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
A high-precision on-chip path delay measurement architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Understanding the effectiveness of their production testsis a critical task for IC suppliers. Numerous trendssuggesting that conventionally applied test methods mustchange to meet future needs will make the task even morecritical - and difficult - in the future. This paper presentscharacterization and diagnostic data and ideas aimed athelping IC suppliers understand test effectiveness.